Building circuits on real chips as test chips can provide insight into how a new fabrication process works. Traditionally, semiconductor manufacturers relied mainly on SRAM (static random-access memory) test chips for ramping up, qualifying and monitoring new semiconductor fabrication processes. The transistor and circuit geometries used on an SRAM test chip, however, represent only a small fraction of the transistor and circuit geometries found in a real product. In recent years, test chips with logic circuit components (logic test chips hereinafter) are often utilized to supplement or replace SRAM test chips. While more closely representing chips with real circuit designs, the logic test chips are not as easily testable or diagnosable as the SRAM test chips.
To check whether a logic test chip is fabricated according to the design and to locate potential defects, scan chains formed by scan cells may be inserted into these circuit designs. Using the scan chains, scan-based testing and diagnosis are performed. Because the scan chains themselves may be defective due to systematic or random manufacturing variations, the integrity of scan chains needs to be checked first before testing the circuit under test.
Scan chains and scan cells are built with logic circuit components and thus may contain transistor and circuit geometries needed for test chips. Moreover, the functionality of a logic test chip is usually not a concern. Therefore, a logic test chip may be constructed mainly with scan chains. Testing such a logic test chip then becomes testing scan cells and their interconnections.